1. Field of the Invention
This invention relates to a cache memory and more particularly to a cache memory which makes a computer system quicker by reducing cache misses.
2. Description of the Related Art
Many conventional cache memories are expensive and have hence been used in only a limited part of the computer system. But as advances have been made in process technology, application of more inexpensive memories has been on the increase recently. Meanwhile the quicker the CPU, the higher the price which had to be paid for cache mistakes; consequently using cache memories would be a key to the performance of computer systems.
The conventional technology for minimizing cache mistakes and making purge and load of data quicker is exemplified by the following prior art:
Japanese Patent Laid-Open Publication No. SHO 60-79446 discloses a concept of putting a task identifier with data to be accessed in the cache memory only when a logical address to be accessed and the task identifier coincide with each other. Japanese Patent Laid-Open Publication No. SHO 62-145341 discloses a concept of dividing the cache memory into a shared space area and a multi-space area so that purge of these divided areas can be respectively controlled. According to these prior concepts, overhead accompanying replacing of cache data is minimized in an effort to make purge and load of data quicker and more effective.
Japanese Patent Laid-Open Publication No. HEI 4-18649 discloses a concept of maintaining data of the designated cache memory area in a simple cache memory for a disc equipment having no LRU algorithm, improving the rate of processing write/read commands.
Under the foregoing circumstances, in order to realize a quick computer system, it should minimize cache mistakes or should effectively use CPU latency for the cache memory.